As the numbers of computers and computer users have grown, the demand for communication between users and machines has correspondingly increased. Computer networks which permit such communication have been constructed which comprise more than one processing element. The processing elements may, for example, include portable or laptop computers, personal computers, minicomputers, or the subsystems internal to each of these types of computers. Typically, each of these processing elements operates asynchronously and independently of others in the network, but is able to communicate with the other processing elements in the network.
Asynchronously operating individual processing elements which are connected to each other in a network may together provide the capability of performing parallel processing. During parallel processing, two or more processes, or functional entities, may be executed concurrently by interconnected processing elements to simultaneously process a large number of tasks.
Connectivity among processing elements in parallel processing networks varies considerably between networks. In some networks, each of the processing elements is connected with every other processing element. In others, only neighboring processors are connected. The media through which the individual processing elements in a network are connected also varies among networks. Some networks capable of parallel processing are built around a bus architecture, in which each of the processing elements is connected to bus over which communications take place. Any one processing element may access memory in another processing unit by accessing and taking control of the bus. In this manner, information may be passed from processing element to processing element via memory which is located on the processing elements or on expansion memory within the system.
Networks built around a bus architecture are typically referred to as tightly coupled, since each processing element in the system is directly coupled to the bus. Because of the potential for synchronization errors in such a system, a bus access control mechanism must be provided to arbitrate between processing elements competing for control of the bus. The bus control mechanism must also ensure that a recipient processing element cannot read before a sending processing element has sent its message, and so that the sending processing element does not begin writing until the recipient has read the last information written.
Loosely coupled systems comprise more than one processing element which include connection by a serial form of interconnection which does not permit one processing element from directly accessing memory on another processing element. Loosely coupled systems, however, permit coprocessing by each of the processing elements concurrently, and further permit message passing. Messages are passed between the processing elements using a protocol which is mutually agreeable to the processing elements. Because of the uncertainty associated with network communications, it is the duty of both the sending and receiving processing elements to confirm the integrity of the communications link. Thus, the protocol typically incorporates an error-detection method. The protocol must also specify the manner in which to initiate and terminate the communications channel. As it is possible that more than one channel may be open at any one time, some form of message differentiation must also be incorporated.
The processing elements in a computer system such as a loosely coupled network may each include more than one active entity or function for performing one or more programs, and associated support hardware. The programs include tasks or instructions suitable for processing by the processor. The programs run applications or input/output (I/O) support, and operate on separate process execution threads. Generally, these programs may communicate with other programs on the same processing element by means of interprocess communications (IPC) software. Communications between programs on loosely coupled separate processing elements, however continues to present design difficulties.
It is an object of the present invention, then to provide logic in the form of hardware support that interfaces between IPC software and the interconnect media in a loosely connected computer system. The hardware support permits individually executing functions on asynchronously operating processing elements within the system to indirectly communicate with memory on other processing elements within the system.